| 摘要 |
The invention relates to a multiplexer for a digital switch, arranged to be included in a switch network whose data flow is organized in frames containing a number of time slots, said time slots including data time slots, which shall be directed through the switch from first to second sets of terminal units, such as subscriber connections, trunk connections, processors, etc. The multiplexer is controlled by a processor for controllable multiplexing, i.e., mapping of a number of transmission links from each of a corresponding number of the terminal units of said first set to a transmission link leading to the switch, as well as of a transmission link leading from the switch to a number of transmission links leading to each of a corresponding number of terminal units of said second set. The mapping is performed on the data time slots. All data time slots arriving from the terminal units of said first set are to be sent forward via a first buffer to the switch in an order which is determined by a first control memory for the mapping, and all data time slots arriving from the switch are to be sent forward via a second buffer toward the terminal units of said second set in an order which is determined by a second control memory for the mapping. The buffers are implemented as fifos, one for each of the links from and to the terminal units. |
