发明名称
摘要 PURPOSE:To improve the reverse withstand voltage at junctions by a method wherein the surface of a P type semiconductor layer is provided with a P type expitaxial layer of low impurity concentration, and an N type impurity is deposited on its surface and then diffused by intrusion into the boundary region of said epitaxial layer. CONSTITUTION:A P type semiconductor layer P2 (gate layer) is formed by diffusing a P type impurity from the surface of an N type semiconductor layer N1. Next, the P type epitaxial layer P<-> of low P type impurity concentration is formed on the surface on this semiconductor layer P2. Then, a deposition layer N<+> is formed by depositing an N type impurity on the surface of this epitaxial layer P<->; thereafter, this impurity is diffused by intrusion to the boundary region between the semiconductor layer P2 and the epitaxial layer P<->. Thereby, an N type semiconductor layer N2 serving as the cathode layer is formed by junction on one surface side of the semiconductor layer P2. Since this manner enables the layer P2 to have the peak of impurity concentration at the part other than the end in the thickness dcirection, the reverse withstand voltage VGR can be increased with the reduction in resistance of the semiconductor layer P2.
申请公布号 JPH0550858(B2) 申请公布日期 1993.07.30
申请号 JP19840136087 申请日期 1984.06.30
申请人 KUSANO MITSUO;MEIDENSHA KK 发明人 KUSANO MITSUO;HANAKURA MITSURU;ISHIBASHI SATOSHI
分类号 H01L29/74;H01L29/744;(IPC1-7):H01L29/74 主分类号 H01L29/74
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