| 摘要 |
PURPOSE:To stable and speed up the pull-in of the PLL by reducing ripples generated in the boundary continuing and disconnecting reference input signals. CONSTITUTION:At the input of a reference input signal Sr, the output of a low pass filter 3 is held in a sample and hold circuit 7 based on the timing signal generated by a sample and hold timing generation circuit 8 to be outputted as the control voltage of a voltage control oscillator 5. Thus, the ripple voltage of the voltage control oscillator 5 at the time of shifting from the disconnection to the continuing state of the reference input signal can be suppressed, resulting in shortening the PLL drawing time. |
