发明名称 CHECK SYSTEM FOR SIGNAL DELAY TIME
摘要 <p>PURPOSE:To calculate the delay value that exactly reflects the inter-clock skew value and to decide a correct critical path by calculating the delay time for each logic and then checking the delay time based on an inter-clock skew value table and in consideration of the inter-clock skew value. CONSTITUTION:An inter-clock skew value table 21 is provided together with a delay check mechanism 3. Then the mechanism 3 starts successively the calculation of delay time at a start point, e.g. FF of each element. Thus each delay time is calculated against a designated junction point, e.g. FF. At the same time, the corresponding inter-clock skew value is taken out based on the table 21. Then this inter-clock skew value is added to the calculated delay time.</p>
申请公布号 JPH05189511(A) 申请公布日期 1993.07.30
申请号 JP19920002538 申请日期 1992.01.10
申请人 FUJITSU LTD 发明人 GOTO KAZUNARI
分类号 G06F17/50;G06F19/00 主分类号 G06F17/50
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