| 摘要 |
PURPOSE:To form the circuit with inexpensive components by devising the cell phase detection circuit such that CRC arithmetic operation is implemented in parallel processing for each block of one byte or the like so as to reduce the circuit scale thereby operating the speed low through the parallel processing. CONSTITUTION:Exclusive OR gates 131-133 execute exclusive OR between input cell data 17 and data 181-183 delayed by one clock at, D flip-flops 121-123 and passing through 8-bit parallel processing CRC arithmetic operation circuits 111-113. Furthermore, a D flip-flop 124 delays output data of the gate 133 by one clock and data 184 are obtained through a parallel processing CRC arithmetic operation circuit 114. Finally a prescribed generation polynomial arithmetic is applied to the entire input cells at an adder circuit 14 and a comparator circuit 15 compares an output 185 of the adder circuit and the inputted cell data 17. |
