发明名称 Sigma-delta-modulaattorijärjestelmä
摘要 The invention concerns a sigma-delta modulator system with two cascade-connected modulators. The quantizing error of the first modulator and an error signal e representing integrated signal estimate error are taken to the second modulator for quantizing, the quantized error signal is derived and subtracted suitably from the delayed output signal of the first modulator. To reduce the noise the quantizing in the second modulator is a negative reconnection of the output power from at least one integration stage 42 to the input of a preceding integration stage 41, and the reconnection loop has at least one delay. <IMAGE>
申请公布号 FI920379(A) 申请公布日期 1993.07.29
申请号 FI19920000379 申请日期 1992.01.28
申请人 RITONIEMI, TAPANI;KAREMA, TEPPO 发明人 RITONIEMI, TAPANI;KAREMA, TEPPO;TENHUNEN, HANNU
分类号 H03M;H03M3/02 主分类号 H03M
代理机构 代理人
主权项
地址