| 摘要 |
The method consists essentially in realizing a connection network as a set of two-stage (temporal and space) matrixes; sectioning said connection network in such a way as to be completely implemented by parts in a distributed fashion in similar or identical devices without the use of any centralized common device; realizing said two stages in such a way as to consent the switching of tributary flows organized also in a mixed way, according to any the MUX paths of the SDH standard by limiting to the lower order VCS (see ETS1 specification), and modifying the frame present at the input of the temporal stage with respect to the one described by the standard in order to allow the equalization of delay introduced on the tributaries interconnected by the temporal stage itself. The circuits including time and space division matrixes and relative connection fork, are characterized in that the temporal stage (T) consists of two time division matrixes (T1, T2) having the first one 63 inputs-63 outputs and the second one 3 inputs-3 outputs respectively, as well as of only one space stage for the frame recomposition. <IMAGE> |
