VERFAHREN ZUM HERSTELLEN VON DURCH ISOLATIONSGRAEBEN GETRENNTEN WANNEN FUER CMOS-TRANSISTOR-SCHALTUNGEN.

摘要

The first well-type is defined using a resist-mask on top of a structure consisting of a thin thermal oxide, an oxide deposited pref. by decompsn. of tetra-ethylortho-silicate (TEOS) and a deposited Si-nitride layer. The mask is used afterwards to assit isotropic etching of the oxide-layer (2) causing a required amt. of undercutting (7), pref. 1 micron wide, of the nitride-layer edge. The etch used is pref. wet-etch. This undercut region (7) determines the width of the moats to be formed, while the depth, pref. 2-3 micron, depends on the time of the anisotropic Si-etching. The moat-etching is pref. carried out after implantation of the first well-type but before that of the 2nd well-type. In order to obtain a level surface in the process the despn. of a polycrystalline Si layer, pref. 200 nm thick, on the first oxide-layer, before depsn. of the TEOS-oxide (2) provides the Si required for oxidn. over the first well-type. The thermal oxidn. of the well-surfaces (14) also diffuses the dopants implanted into the wells (5,12).