| 摘要 |
A voltage variable delay circuit that provides a relatively constant delay independent of operating voltages, temperatures or processing variations is disclosed. The circuit is particularly suited for delay line or oscillator applications. The relatively constant delay is accomplished by accurately controlling the switching speed of each of the complementary series arranged inverter elements used for the delay line or oscillator. The accurate control is provided by first and second high impedance inverters connected to the gate electrode of series arranged inverters. In the delay line application, two similarly fabricated series arranged inverter elements are placed in parallel. One of the series arranged inverters is used as an operating circuit and the other is used as a reference circuit. A clock signal is used to synchronize the reference circuit with a timing network, and a comparator is used to measure the time difference between the reference circuit and the timing network. The output of the comparator is integrated and used to produce an analog-type control voltage which varies the time delay of both the operating and reference circuits until the reference circuit time delay is equal to that determined by the timing network. Conforming the reference circuit also conforms the operating circuit thereto. In the oscillator application, a synchronizing circuit is also used to produce a variable control voltage that adjusts the oscillator frequency until it is equal to an external measuring synchronizing time base.
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