发明名称 Method for fabricating an interconnection pattern on a BPSG-filled trench isolation structure
摘要 A semiconductor device is provided with an isolation region for isolating the semiconductor device from an adjacent semiconductor device provided commonly on a semiconductor substrate. The isolation region includes a groove extending to a predetermined depth of the substrate, a non-doped silicon oxide layer provided on a whole inner surface of the groove, and a BPSG (boro-phosho-silicate glass) layer filled in a remaining portion of the groove covered with the non-doped silicon oxide layer on the inner surface. An interconnection layer is provided on the isolating region selectively.
申请公布号 US5231046(A) 申请公布日期 1993.07.27
申请号 US19920879302 申请日期 1992.05.07
申请人 NEC CORPORATION 发明人 TASAKA, KAZUHIRO
分类号 H01L21/76;H01L21/311;H01L21/762;H01L21/768 主分类号 H01L21/76
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