发明名称 Digital multiplier based upon a regularly structured sum of products adder array for partial product reduction
摘要 A digital multiplier is configured from a number of identical circuit "slices" with interconnecting signals arranged such that the need for large wiring channels is eliminated. The resulting multiplier, a hybrid of tree and array multipliers, has many of the space saving characteristics of array multipliers, with many of the speed advantages of tree multipliers. Various parameters of the design are flexible and may be changed by the designer to make speed versus size tradeoffs. The multiplier may be either pipelined or non-pipelined.
申请公布号 US5231601(A) 申请公布日期 1993.07.27
申请号 US19920827576 申请日期 1992.01.28
申请人 LSI LOGIC CORPORATION 发明人 STEARNS, CHARLES C.
分类号 G06F7/52 主分类号 G06F7/52
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