| 摘要 |
PURPOSE:To provide the extension circuit in which number of handled signal lines is extended with simple circuit configuration and number of bits of frame synchronizing signal is increased. CONSTITUTION:The extension circuit is provided with a memory circuit 1 storing a data signal and outputting it, a flip-flop circuit 5 latching the data signal and outputting the latched delay signal SBO, a reset circuit 4 outputting a feedback signal in response to the latched delay signal SBO and a reset signal SR, an OR circuit 3 ORing the feedback signal and an input signal SB1 and outputting an OR signal S, representing the OR of the signals, a latch circuit 2 latching the OR signal SD in a high impedance and sending the OR signal SD to the memory circuit 1 as a data signal, and a decoder circuit 6 giving an address for the data signal to the memory circuit 1. |
