| 摘要 |
<p>PURPOSE:To shorter an excessive processing time generated due to the misreading cache by inhibiting the operation of a cache memory by a cache inhibiting signal outputted from a cache inhibition signal output part. CONSTITUTION:In the case of inhibiting the operation of the cache memory 11, information specifying a specific instruction is stored in a cache inhibiting instruction specifying field 6, the specified specific instruction is executed based upon the stored information and a cache inhibition signal is outputted from a cache inhibition signal output part 4. Thereby the operation of the memory 11 is inhibited. If all data to be read out are not stored in the memory 11 in the case of successively reading out plural continued data stored in continued addresses by a microprocessor 9, the operation of the memory 11 is inhibited by executing the specific instruction specified by a user and plural data of the continued addresses are read out from a main memory 10.</p> |
