| 摘要 |
PURPOSE:To output a correct recovered clock regardless of the stop or operating state of a receiver by outputting a sum output signal of 1st and 2nd LPFs or an output of the 2nd LPF as a control signal when an input signal is impressed or not impressed to a phase comparator respectively. CONSTITUTION:A phase comparator 111 detects a phase difference of an input signal impressed intermittently and an output of a VCO 13 and sends the result to LPFs 12, 21 via a charge pump circuit 112. The circuit 112 includes a capacitor and charged by a phase difference voltage while the phase difference signal is received. On the other hand, the LPF 12 extracts a voltage VAC corresponding to the phase difference and the LPF 21 extracts a DC voltage VDC. While the input signal is received, a switch SW is closed, the signals from the LPFs 12, 21 are added by an adder 32, the result is fed to the VCO as a control signal, from which a recovered clock signal is obtained. While no input signal is received, an input signal detector 31 detects it to turn off the SW, and an output of the LPF 21 is fed to the VCO 13. Thus, the synchronization is attained in a short pull-in time in the succeeding operating state of the receiver. |
