| 摘要 |
PURPOSE:To obtain a data delay circuit which is variable in delay quantity and enables a multi-stage delay circuit to consist of a small number of components as to a data delay circuit used for an image processor, etc. CONSTITUTION:This data delay circuit is constituted having a memory 10, a write address generating means 2, a read address generating means 3, an address bus switch 4 which selects the write address generating means 2 or read address generating means 3 and specifies the address of the memory 10, an input data latch 6, an output data latch 7, a data bus switch 8 which forms the path from the input data latch 6 to the memory 10 or the path from the memory 10 to the output data latch 7, and a control circuit 1 which controls the operation of the constituent elements of the data delay circuit with a clock signal having the unit delay time of the data delay circuit as one cycle. |
