发明名称 ERROR RETRY SYSTEM
摘要 PURPOSE:To execute re-reading without fail when error is detected during data transfer by storing read data in a data buffer for the access time of a module. CONSTITUTION:A CPU 11 accesses a module 21 (S1) and reads required data (S2). At this time, the module 21 stores data having the same contents as these read data in a data buffer 23 loaded on the module board. When there is no error in the read data, the CPU 11 starts the other processing as it is and when the data error is detected (S4), however, the data buffer 23 is accessed (S5). Therefore, the CPU 11 reads data similar to the last time from the data buffer 23 again (S6). Thus, the data error can be dealt with during the data transfer from the module 21 to the CPU 11.
申请公布号 JPH05181690(A) 申请公布日期 1993.07.23
申请号 JP19910357632 申请日期 1991.12.26
申请人 OKI ELECTRIC IND CO LTD 发明人 JINNAI HIDETO
分类号 G06F11/00;G06F11/14 主分类号 G06F11/00
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