SERIAL DATA SEPARATION CIRCUIT

摘要

PURPOSE:To reduce circuitry by latching n-bit serial data in the unit of m-bits and thereby separating data every time of m-stage-shifting the n-bit serial data by an m-bit shift register. CONSTITUTION:An 8-bit shift register 11 shifts 72-bit serial data by 8 stages and outputs the result as a parallel signal. A counter 12 receives a frame pulse L and a clock pulse CK to count 8-bits, a decoder 13 receives an output from the counter 12 and outputs the clock used to latch the 8-bit parallel signal outputted from the register 11 for each 8-bit to 9 points. An FF 14 receives a parallel signal from the register 11 to latch the signal for each 8-bit based on a latch clock from the decoder 13 and the result is outputted as the 8-bit parallel signal. A selector 15 selects one parallel signal among the 8-bit parallel data sent from the 9 points and outputs the selected signal.