| 摘要 |
PURPOSE:To attain the data communication service without error by eliminating deficiency or excess of a data signal depending on the difference of a clock source between a transmission line network and a data device. CONSTITUTION:In data device connection units 2 arranged opposite to a transmission line network through which data are sent while the data are divided into blocks of a prescribed length, a speed variable speed circuit 26 monitors the storage quantity of outgoing data block in a transmission speed conversion circuit (buffer memory) 25 and controls variably a frequency division ratio of a frequency divider 24 so that the frequency of a timing clock (RT) of reception data (RD) is higher than a frequency corresponding to the nominal transmission speed of the data unit 2 connecting to its own unit when the storage quantity of the data blocks exceeds a reference quantity and controls variably the frequency division ratio of the frequency divider 24 so that the frequency of the timing clock (RT) of reception data (RD) is smaller than the frequency corresponding to the nominal transmission speed of the data unit 2 connecting to its own unit when the storage quantity of the data blocks are less than the reference quantity. |
