| 摘要 |
Clock signals for determining the edge timing of a driver output waveform are generated by a timing generator (300). Pattern data and control data for selecting a waveform mode in real time in synchronism with the pattern data are generated by a pattern generator (200). An enable data generating circuit (103) generates an enable data to determine whether the A, B, and C clock signals ACK, BCK, and CCK for determining the edge timing of the driver output waveform is used or not on the basis of selected one of the waveform modes stored in a storage (105), and of the pattern data. A waveform generating circuit (106) generates a driver output waveform in accordance with the enable data and the A, B, and C clock signals. |
