| 摘要 |
<p>A circuit for dividing a master clock by an odd integral value and producing a 50% duty cycle. A state machine develops set and clear signals which are of a timing proportion of n: n + 1, where 2n + 1 is the divisor value. The set signal is provided to one input of a bistable multivibrator or S-R latch to set the multivibrator to a given state, while the clear signal is combined with the master clock signal to delay or disable the clearing of the multivibrator by 1/2 count of the master clock, so that an n + 1/2 : n + 1/2 proportion output clock signal is developed. Additionally, the circuit includes a state machine which determines which of a series of differing frequency master clock signals is active and when an external triggering event occurs so that the following rising edge of the output clock signal is delayed until a determined time after the triggering event to allow synchronization of the output clock signal.</p> |
