| 摘要 |
<p>A numeric data coprocessor having an execution unit adapted to efficiently execute the ADD/SUB operations on floating-point numbers in compliance with the IEEE standard 754. According to the basic principles of the present invention, the mantissa adder carry out bit resulting from the operation on two operands X and Y is directly concatenated with the mantissa adder results in the mantissa output register to be the MSB thereof. Simultaneously, a one is added to the exponent of operand X or Y of the greatest magnitude. Consequently, the final result, is found after normalization regardless the carry out bit is equal to 1 or 0. From an hardware aspect, taking for example the 80-bit double extended precision IEEE format, the mantissa ouput register (33) has 68 positions. The 68th supplementary position is fed by the carry out bit generated by the mantissa adder (17) at the "carry out" output (CO). In addition, the "Force Carry" input (FC) of the exponent adder (16) is activated by the control logic circuitry to add a one to the operand exponent of the greatest magnitude. As a result, with respect to the conventional method and apparatus, the step of mantissa and exponent correction, which requires a great number of machine cycles is bypassed, and some hardware is eliminated. <IMAGE></p> |
