ADDRESS TRANSITION DETECTING CIRCUIT

摘要

The circuit for using a transmission gate to reduce the layout size and to obtain an address transition detection signal without current loss comprises a delay chain (3) having inverters to generate a predetermined pulse width, an inverter chain (4) having inverters (I1,I2) connected between an address buffer (AB) and the delay chain, and an address transition detection signal generator (5) having a first transmission gate (T1) connected to the address buffer (AB) and a second transmission gate (T2) connected to the inverter (I1).