| 摘要 |
<p>There is disclosed a circuit arrangement to permit reduction of the occupation area and the power consumption in a complementary logic circuit constituting a sequence circuit such that it is used in a manner switched between ON state and OFF state. This circuit arrangement as a sequence circuit comprises a delay circuit 2 comprised of a group of D flip-flops of the dynamic type and a combination circuit 1 connected to the delay circuit, thus to allow all inputs of the combination circuit 1 to be compulsorily brought into a predetermined state during an operation stop period of the delay circuit by an input control circuit 3, and to allow the delay circuit to be placed in a data through condition, with each of master and slave latches of the group of flip-flops constituting the delay circuit being caused to be inoperative or inactive, by an operation stop control circuit 4. <IMAGE></p> |
