发明名称 Bit synchroniser for use in systems with very high clock rates
摘要 The invention relates to a device for correcting phase differences between binary signals which contains one phase detector each for the phases of the signals and a phase shifter for changing the phases of one of the two signals. Two integrators are provided, at the inputs of which in each case one of the two signals is present. A comparator receives two reference voltages and the integration signal and outputs at its output a control signal proportional to the difference between the integration signals and thus to the phase difference between the two signals as input for the controlled phase shifter. <IMAGE>
申请公布号 DE4305244(A1) 申请公布日期 1994.08.25
申请号 DE19934305244 申请日期 1993.02.20
申请人 MAZ MIKROELEKTRONIK-ANWENDUNGSZENTRUM HAMBURG GMBH, 21079 HAMBURG, DE 发明人 ZHANG, CHEN-XIONG, 2150 BUXTEHUDE, DE
分类号 G01R25/04;H04L7/033;(IPC1-7):H03K5/135;H03K5/26;H03L7/08;H04L7/00;H04L25/38 主分类号 G01R25/04
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