Data transfer system in which data is transferred to or from a data memory during an instruction fetch cycle

摘要

A data transfer system has an address bus and a data bus, each divided into two parts by a bus switch. A microprocessor and program memory are connected to the first parts of the address and data buses. A data memory, data transfer controller, and input/output devices are connected to the second parts of tile address and data buses. While the microprocessor is fetching an instruction from the program memory, the bus switches disconnect the two parts of the buses, enabling the data transfer controller to transfer data directly between the data memory and input/output devices. At other times the bus switches connect the two parts of the buses, enabling the microprocessor to access the data memory and Input/output devices.