Difference circuitry for image processing - stores first binary signal in MOS cell, selectively inverts second signal and outputs signal if two binary signals have different values

摘要

The circuit consists of a MOS memory cell formed from transistors (T1,T2,T3,T4) which are driven by select lines (b,bN). The stored value in the memory cell is combined with the value input by (b,bn) to generate a half-adder function with outputs (D,DN). The circuit is planned as a building block for large arrays to perform a difference function for image compression by generating difference terms from successive display images, in order to generate a motion estimate of the image. ADVANTAGE - Uses MOS cell which is already present for storing binary signal, for providing output signal.