Advanced low RC multi-level interconnect technology for high performance integrated circuits.

摘要

A novel "low-RC multi-level interconnect" technology has been conceived for advanced sub-0.5 mu m silicon technologies. The proposed process has a number of significant characteristics: (i) compatible with various metal systems (Al, Cu, W, etc.), (ii) "air-gap" interlevel dielectrics; (iii) compatible with standard fabrication processes, (iv) excellent mechanical stability; and (v) compatible with hermetically sealed packaging techniques. Compared with a Al-based advanced interconnect technology, the new interconnect system can reduce the RC delay by a factor of 6. The impacts are major chip performance improvements such as lower power dissipation and higher operation frequencies. This technology extends the air-gap technique well into the Si domain and is a technology scaling enabler.