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摘要 <p>PURPOSE:To reduce the number of elements and to attain high integration by using the load of a NAND gate as a constant current source based upon a depression type FET and driving an inverter directly by the output of the NAND gate. CONSTITUTION:The load of the NAND gate using Qn1-Qn3 as a driving FET is used as the depression type n-channel MISFET-Qnd and Vppi is used as a power supply for the NAND gate to drive CMOS inverters (Qp3, Qn5) directly by the output X of the NAND gate. Therefore, Qnd is used as a constant current load and VSS can be precisely obtained by the Qn1-Qn3 having proper size at a selection time. Consequently, layout with narrow pitches can be attained and high integration can be obtained.</p>
申请公布号 JPH0546639(B2) 申请公布日期 1993.07.14
申请号 JP19840166114 申请日期 1984.08.08
申请人 FUJITSU LTD 发明人 YOSHIDA MASANOBU
分类号 G11C11/413;G11C11/34;G11C16/06;G11C17/00;H01L21/8238;H01L27/08;H01L27/092;(IPC1-7):G11C16/06 主分类号 G11C11/413
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