| 摘要 |
PURPOSE:To enable a PE-to-PE communication and improve processor performance. CONSTITUTION:The parallel processing system consists of plural PEs 1a, 1c, and 1d and a network 2 which connects the PEs mutually. The PE 1a is constituted by connecting a processor 3a, a memory 4a, and a data transfer device 5a to a common bus. The data transfer device 5 has three buffers and a data repeating device 6 has two buffers. Data from the PE1a to the PE1d are transferred in the order of the memory 4a, buffer 7a, buffer 10a, buffer 8c, buffer 11e, buffer 9d, and memory 4d as shown by a dotted line. Namely, the PE1c repeats the data by utilizing the buffer 8c. Consequently, neither memory writing nor reading is performed at the repeating PE at the time of an optional PE-to- PE communication, so the overhead at the repeating PE is reduced to improve the transfer performance. Further, the data transfer device performs no bus access, so the bus width is widened and the performance of the processor is improved. |
