发明名称 LOAD LOCKING CHAMBER OF SEMICONDUCTOR PROCESSING DEVICE
摘要 PURPOSE:To enhance the throughput, simplify the mechanism, and ensure the reliability by providing a rotary table on which a plurality of cassettes can be placed, and installing a plurality of gate valves or the like. CONSTITUTION:Through a gate valve or valves 11, a plurality of cassettes 101-104 or the like are fed from the atmosphere and installed onto a rotary table 2 arranged in a load locking chamber 1. The valve 11 is then shut to evacuate the load locking chamber 1, and with the table 2 rotating one turn, wafers in the cassettes 101-104 are transported to a processing chamber 152, etc., separately or simultaneously to undergo processing there. This permits increasing greatly the number of wafers in the cassettes on the table 2 capable of being vacuum processed during one run of evacuation of the load locking chamber 1 and also allows the chamber 1 to be embodies relatively small. Further the wafers can be vacuum processed continuously and automatically to give a high throughput, and also suppressing space and stabilized operation are established and the economy is enhanced.
申请公布号 JPH05174776(A) 申请公布日期 1993.07.13
申请号 JP19910337341 申请日期 1991.12.20
申请人 HITACHI LTD 发明人 USAMI YASUTSUGU
分类号 C23C14/56;B65G49/07;H01J37/317;H01L21/00;H01L21/677 主分类号 C23C14/56
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