INTEGRATED CIRCUIT WITH INCORPORATED CLOCK SKEW ADJUSTING CIRCUIT

摘要

PURPOSE:To adjust the delay time of distribution up to a register through a clock terminal and to substantially eliminate a skew. CONSTITUTION:This circuit is equipped with plural input buffer gates G1 and G2 for distributing an inputted clock signal, a 1st selecting circuit SL1 which varies the number of states of the input buffer gates G1 and G2, a delay circuit 20 which varies and sets the delay time of the clock signal through an external control terminal, and a clock distributing circuit 21 composed of plural gates so as to distribute the delay-controlled clock signal to plural registers. Further, the circuit is equipped with a 2nd selecting circuit SL5 which inputs the outputs of the input buffer gates G1 and G2 inputting the clock signal and one output of the clock distributing circuit 21 and selects either one through the external control terminal.