| 摘要 |
<p>PURPOSE:To attain rapid data processing in a small circuit size by dividing an over lapped orthogonal transformation(LOT) processing so as to include an arithmetic means capable of executing operation in a closed block and an arithmetic means capable of executing operation by plural blocks. CONSTITUTION:At the time of LOT operation, a discrete cosine transformation(DCT) operation output is Hadamard-transformed by a Y1 stage 22. The even side of Hadamard-transformed outputs is directly inputted to a Y2 stage 23 and the odd side is temporarily stored in an one-block line memory 24. At the succeeding timing, the odd side stored in the memory 24 is inputted to the Y2 stage simultaneously with the input of the even side to the Y2 stage 23 and both the inputs are Hadamard-transformed. An output from the Y2 stage 23 is inputted to a Z stage 25 to obtain an LOT operation result. At the time of inverted (I) LOT operation, input data are computed by the Z stage 25 and Hadamard-transformed by the Y2 stage 23 and the even side of the transformed result is directly outputted.</p> |
