发明名称 MONITOR CIRCUIT FOR WATCHDOG TIMER
摘要 PURPOSE:To correctly detect whether both a corresponding central processing unit 1 and a watchdog timer operate always normally or not through simple circuit configuration. CONSTITUTION:In a circuit constituted of the watchdog timer 2 connected to the central processing unit 1 and a capacitor voltage detecting means 4 which compares the voltage of a capacitor 3 connected to the watchdog timer 2 with the prescribed voltage and informs the central processing circuit of this result, the pulse P of a prescribed period is generated from the central processing unit 1 to the watchdog timer 2, and simultaneously, the watchdog timer 2 is provided with a means to generate a reset pulse RP to the central processing unit l when the pulse from the central processing unit 1 does not come, and further, the capacitor voltage detecting means 4 includes the means to inform the central processing unit 1 of information based on relation between the voltage of the capacitor and the prescribed reference voltage and informing whether the watchdog timer 2 operates normally or not.
申请公布号 JPH05173841(A) 申请公布日期 1993.07.13
申请号 JP19910345282 申请日期 1991.12.26
申请人 FUJITSU TEN LTD 发明人 KINOSHITA KENICHI
分类号 G06F11/00;G06F11/30 主分类号 G06F11/00
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