发明名称 FRAME PHASE SYNCHRONIZING METHOD AND CIRCUIT
摘要 PURPOSE:To allow the circuit to cope with a revision of a pointer of a reception frame at a high speed by calculating a pointer value of a transmission frame through the use of a phase difference between the reception frame and the transmission frame and a pointer of the reception frame. CONSTITUTION:A reception frame counter 16 counts an offset address of a frame, a detection circuit 17 detects a pointer representing a head position of user information in a frame and stores it to a buffer 18. Moreover, a transmission frame counter 19 counts an offset address of the frame and a registration 20 stores an offset value. An adder/subtractor 21 adds/subtracts values of the buffer 18 and the registration 20 and sends a pointer value to a selector 22. The selector 22 multiplexes the pointer, the frame synchronizing signal given separately, an overhead bit and user information in the memory 12 and outputs the result. Thus, the pointer value of the transmission frame is revised at a high speed with respect to the revision of the pointer of the reception frame.
申请公布号 JPH05175929(A) 申请公布日期 1993.07.13
申请号 JP19920122171 申请日期 1992.05.14
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 ICHIMORI MINEKI;FUKAMI KENNOSUKE;KATAOKA HIDEKI
分类号 H04J3/06;H04J3/00;H04L7/00;H04L7/08;H04L25/52 主分类号 H04J3/06
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