发明名称 TIMING CIRCUIT FOR DIGITAL TRANSMISSION SYSTEM
摘要 PURPOSE:To allow the circuit to cope with a signal transmission system even in a digital signal transmission system by any form of a band pass filter timing circuit section or a PLL timing circuit section. CONSTITUTION:The digital transmission system timing circuit equipped to a reception terminal station is provided with a band pass filter timing circuit section 4 and a PLL timing circuit section 5 and any of the band pass filter timing circuit section 4 or the PLL timing circuit section 5 is selected by a changeover circuit section 6 based on the quantity of jitter in a sent data string.
申请公布号 JPH05175948(A) 申请公布日期 1993.07.13
申请号 JP19910356188 申请日期 1991.12.24
申请人 NEC CORP 发明人 MATSUMOTO YOSHIHIRO
分类号 H04L7/027;H04L7/033;H04Q11/04 主分类号 H04L7/027
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