发明名称 METHOD FOR PREPARING INSPECTION PATTERN OF COMBINATORIAL LOGIC CIRCUIT
摘要 PURPOSE:To improve the inspection pattern preparing efficiency of the title method by adding a label on which the kind of a fault difference is described and updating the label of the output line of a logic element with a changed signal value, and then, assigning the fault difference and time signal value on the updated label. CONSTITUTION:When attention is paid to the output line (e) of an AND gate 11, a possibility of propagating a fault difference to the line (e) exists and (+) is given as a label, because 'D' is inputted to the input signal line (b) of the gate 11 as the fault difference. A label (+) is given to the output signal line (f) of another AND gate 12 in the same way and a label (-) is given to the output line (g) of a NOT circuit 13 by negating the output of the circuit 12. When '1' is assigned to a signal line (a) and 'D' is propagated through the signal line (e) while an inspection pattern preparing algorithm is forwarded, the input lines (d), (e), and (i) of an OR gate 15 for unique activation are checked and the 'D' is not propagated through the signal line (i) having the (-) label, but 'O' is given to the line (i). As a result, the signal values of signal lines (g), (h), and (f) are found through normal agreeable operation.
申请公布号 JPH05172905(A) 申请公布日期 1993.07.13
申请号 JP19910344708 申请日期 1991.12.26
申请人 TOSHIBA CORP 发明人 URUCHIDA HIROSHI
分类号 G01R31/3183;G01R31/28;G06F11/22;G06F17/50 主分类号 G01R31/3183
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