Synchronous communication interface for reducing the effect of data processor latency

摘要

Incoming data which is required to be passed to a desired storage location under the control of a processor is received by a store prior to being passed to a serial communications controller. The store is preferably a FIFO store and stores the data at an incoming data rate determined by the incoming transmission line data rate and feeds the data to the serial communications controller at a higher data rate under the control of a clock generator which is energized by control circuitry only when the serial communications controller indicates that it is able to accept the data. The processor can therefore control the serial communications controller to cease to process incoming data, which data is then stored until the processor can spare the time to recommence processing the incoming data.