| 摘要 |
A semiconductor memory adapted to receive a chip selection signal and address signal, composed of: a signal generating circuit for generating inner selection signals with respect to the chip selection signal, a pulse generating circuit for detecting any changes in the address signals and generating a pulse signal; and a pulse width changing circuit for inputting the pulse signal to output a control signal for precharging or equalizing the data lines of a memory cell array. The pulse width changing circuit outputs the control signal having a pulse whose pulse width corresponds to what is obtained by converting the pulse width of the pulse signal into a longer one when the inner selection signals are in the chip-selecting condition.
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