Low voltage supply non-volatile memory reading circuit for GSM communications

摘要

The circuit includes a selection transistor (SS) in series with a floating gate transistor (TGF) and a bit line (LB). The gate of the selection transistor is connected to a word line (LM) while the gate of the second transistor is connected to a reading line (LL). The information read from a memory cell (CM) is delivered through the bit line. A reference transistor (T3), provided in a current mirror, has its source connected to a supply voltage (Vcc). A delay between its drain and gate voltage is introduced by a transistor (T5) in series with a supply transistor (T6).