SIGNAL DELAY CIRCUIT

摘要

The circuit for improving the operation speed due to a delay characteristic independent of fluctuations in the voltage supplied includes a driving unit (DRV) connected between a supply voltage (Vcc) and a ground potential (Vss) and having a pull-up PMOS transistor (PM) and a pull-down NMOS transistor (NM) with respective predetermined threshold voltages. The driving unit provides an output signal (Vo) having a voltage swing between the Vcc and Vss to a common drain node of the transistors in response to at lease one input signal (VIN). A varactor load unit (VCL) is coupled to the common drain node, having a capacitance which increases according to the increase of the output signal voltage of the common drain node within a variation range from the threshold voltage of the pull-down NMOS transistor to the supply voltage.