Lock detector for a phase locked loop.

摘要

Lock detector for a phase locked loop (PLL) in which a phase error signal (y) is generated representing the phase difference between a reference signal (Fref) and a signal (F) to be locked onto the reference signal. The detector comprises means (42) making it possible to provide the derivative ( phi ') of the phase error signal ( phi ) and a comparator (44) activating a locked detection signal (LD) when the amplitude of the said derivative ( phi ') is below a predetermined threshold ( phi '0). The means comprise an up/down counter (54) for counting up and counting down a clock of high frequency with respect to the frequency of phase error pulses generated by the phase detector of the PLL. The counting up or counting down mode of the counter is switched alternately from one to the other with each phase error pulse. The counter therefore contains the sum of the width differences of the successive pulses generated by the phase detector. <IMAGE>