发明名称 BUS INTERFACE LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE
摘要 A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit. The predetermined set of operating conditions occur when (i) the memory controller on behalf of the central processing unit writes data to the input/output device, or (ii) the memory controller on behalf of the central processing unit initiates a read or write cycle destined for the input/output device acting as a slave on the input/output bus, and the data bus width of the memory controller is greater than a corresponding data bus width of the input/output device. <IMAGE>
申请公布号 AU2979592(A) 申请公布日期 1993.07.08
申请号 AU19920029795 申请日期 1992.12.02
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ALFREDO ALDEREGUIA;NADER AMINI;RICHARD LOUIS HORNE;TERENCE JOSEPH LOHMAN;CANG NGOC TRAN
分类号 G06F13/36;G06F13/16 主分类号 G06F13/36
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