发明名称 PACKET MAJORITY DECISION CIRCUIT
摘要 <p>PURPOSE:To remarkably reduce the number of memories. CONSTITUTION:Data Sb are outputted through a switch SW1 by inputting packet data D1-D2n-2. A counter CNT counts output data from the switch SW1 at every bit by using the data Sb as initial data. Memories RAM1-RAMm store output data from the counter CNT corresponding to each digit of a binary number, add the data at every bit and output the data Sb. A data converter CNV receives the data Sb and outputs data (v) based on a threshold level [n/(2n-1)]. A switch SW2 switches the data (V) and the packet data D2n-1 based on the data Sb and the selected data are outputted from the switch.</p>
申请公布号 JPH05167615(A) 申请公布日期 1993.07.02
申请号 JP19910327791 申请日期 1991.12.11
申请人 NEC CORP 发明人 UMEMOTO AKITO
分类号 H04L1/00;H04L1/08;H04L12/70 主分类号 H04L1/00
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