| 摘要 |
PROBLEM TO BE SOLVED: To process the cancel of instruction fetch without waiting for wasteful data transfer and to give a next instruction fetch request in a case when a processor 1 executing instruction fetch issues the transfer request of an instruction string from a main storage device owing to a cache error, instruction fetch is detected to be a non-branch instruction and it is canceled. SOLUTION: The number of entries in an instruction line transfer buffer 200b in a bus control circuit 200 is larger than the number of entries in an instruction fetch buffer in a branch control circuit 100. In the buffer, bits (CAN bits) showing that the cancel processing of instruction fetch is held are installed for respective entries, A detection circuit for suppressing a next instruction fetch request when the CAN bits are registered in the whole number of entries in the instruction line transfer buffer 200b is installed. Furthermore, a circuit for suppressing instruction fetch data transferred from a main storage controller 2 with the CAN bits is installed.
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