| 摘要 |
A system and method for providing master and slave phase-aligned clocks. Upon a failure of a master clock signal, the system switches over to a slave clock signal in phase alignment with the master clock signal. The master clock signal is from a first clock source, while the slave clock signal is from a second clock source. The second clock source comprises a phase locked loop (PLL) including a switch, which is coupled to selectively provide a control signal to a voltage controlled oscillator (VCO). The switch may also provide a reference control voltage to the VCO. The first clock source may be on a first clock board, and the second clock source may be on a second clock board. The clock boards are preferably hot swappable. The first clock board may be removed from the system, such as upon a failure, and a third clock board placed in the system. The second clock board is switched from being the slave clock source to the master clock source, while the third clock board is configured to operate as the slave clock source. The method provides a first clock signal as a master clock signal. A second clock signal is provided as a slave clock signal, with the slave clock signal phase aligned with the master clock signal. Upon a failure of either the master clock signal or the slave clock signal, a user is notified of the failure. Upon the failure of the first clock signal, the second clock signal is switched in place of the first clock signal as the master clock signal. Clock switching is automatic and does not interrupt or interfere with operation of the computer system. |
