发明名称 Memory array with address scrambling
摘要 A memory array includes a plurality of storage cells (10) and a selection device (14) which selects a storage cell (10) for physical access due to a logical address (23) supplied via an address bus (20). The selection device (14) includes a scrambling device (15) which allocates a storage cell (10) in the memory array in predictable fashion by scrambling to a logical address (23) transmitted to one of the selection devices (14), the cell then being physically accessed.
申请公布号 AU4921100(A) 申请公布日期 2000.12.05
申请号 AU20000049211 申请日期 2000.05.11
申请人 GIESECKE & DEVRIENT GMBH 发明人 MICHAEL BALDISCHWEILER;STEFAN ECKARDT
分类号 G06F12/14;G06F21/24;G06K19/073;G07F7/10;G11C7/00;G11C8/00 主分类号 G06F12/14
代理机构 代理人
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