| 摘要 |
<p>PURPOSE: To test a digital processor at the maximum operation speed, by mounting an IC for high speed test which has a digital processor, on a joint tester action group(JTAG) test port, and transferring a test program. CONSTITUTION: Programmable digital processors 21, 23, 24 and a P-ROM 22 constitute a digital processor. A test data register(TDR) 11 receives a test program via a serial test input port(TDI), and has (n) bit positions for transferring the test program, in the P-ROM 22. A test control register(JCOM) 10 executes block down loading of the test program on a TDR 11 under the control of a finite-state machine of JTAG and a command decoder, and makes the test program be received as continuous sequence of data words. The degital processor outputs the result of a processed program from a serial test output port TDO, via TDR 11.</p> |
