发明名称 WATCHDOG TIMER CIRCUIT
摘要 PURPOSE:To detect the runaway of a CPU while it has an access to a memory means with a watchdog timer circuit which is used to a monitor controller. CONSTITUTION:When a CPU 2 has no access to 1 storage means 4 even in a normal operation state of the CPU 2, a watchdog timer circuit 3 is repetitively reset before the set time is counted with the reset commands impressed periodically from the CPU 2 and then counts the set time if the reset commands received from the CPU 2 are delayed and transmits an alarm to show the runaway of the CPU 2. Meanwhile 8 data collator means 5 transmits the reset signals to the circuit 3 every time a fact that the state information on the means 4 read out by the CPU 2 with an access given to the means 4 can receive an access is detected.
申请公布号 JPH05158746(A) 申请公布日期 1993.06.25
申请号 JP19910327186 申请日期 1991.12.11
申请人 FUJITSU LTD 发明人 SAITO HIROYUKI
分类号 G06F11/00;G06F11/30 主分类号 G06F11/00
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