| 摘要 |
PURPOSE:To prevent a cycle slip by preventing mis-operation of detection of a preamble bit change point by establishing frame synchronization with a clock whose phase is controlled after a preamble bit string is normally detected. CONSTITUTION:Reception signals 101 are configured of the same bit structure and have preamble, frame and data bits and a change point detection section 2 detects a change point of the signal from a preamble bit of the signal 101. A control section 3 controls an output clock of the control section 3 among n-sets of polyphase clocks generated in a detection timing of the detection section 2 so as to allow the output clock to take an optimum phase with respect to the phase of the signal 101. The detection section 1 detects a preamble bit string from the signal 101 inputted via an AND circuit 8. The output 103 opens an AND circuit 9 and a control section 4 controls a clock phase when the preamble bit string is normally detected. A frame counter 6 and a frame detection section 5 use an output 108 of the control section 4 to establish frame synchronization with respect to the signal 101. |
