| 摘要 |
<p>PURPOSE:To miniaturize a device by enabling contention control over a write phase and a read phase while using a single-port RAM. CONSTITUTION:The clock crossing-over circuit, provided with a series-parallel converting circuit 21 which performs series-parallel conversion from series data to parallel data with a 1st clock, the single-port RAM 22 wherein the parallel data from the serial-parallel converting circuit 21 are written, and a parallel-serial converting circuit 23 which performs parallel-serial conversion from data read out of the single-port RAM 22 to series data with a 2nd clock, is provided with a register 24 which is interposed between the single-port RAM 21 and parallel-serial converting circuit 22 and temporarily stored with the read data from the single-port RAM 21 to the parallel-serial converting circuit 22 and a contention control circuit 25 which delays a read of the single-port RAM 22 and writes the read data in the register 24 when the write timing of the single-port RAM 22 conflicts with the read timing.</p> |
